The present invention generally relates to dual-port semiconductor memory devices, and more particularly to a dual-port dynamic random access memory device having a serial input/output circuit part with a simple circuit construction.
As one type of memory device, there is the so-called dual-port (or two-port) random access memory (RAM) which is accessible via two ports. There is a known dual-port static RAM (SRAM) wherein word lines and bit lines are provided in duplex with respect to a memory cell array of the SRAM, and a row address decoder, a column address decoder and the like are provided for each of two groups of word lines and bit lines. On the other hand, there is a known dual-port dynamic RAM (DRAM) wherein a shift register or a serial access memory is provided with respect to a memory cell array of the DRAM.
In other words, the bit lines of the memory cell array of the dual-port DRAM are coupled to corresponding stages of the shift register. Stored data in all of the memory cells belonging to a word line are obtained via the bit lines by selecting the word line. The data can be obtained serially from the shift register by entering the data from the bit lines to the shift register in parallel and successively shifting the entered data. On the other hand, write-in data can be entered serially into the shift register by successively shifting the write-in data. The data can be written into all of the memory cells belonging to a selected word line by simultaneously supplying the data from the shift register to the bit lines in parallel. Hence, input/output terminals of the shift register are coupled to one port of the dual-port DRAM, and normal input/output terminals for the memory cell array are coupled to the other port of the dual-port DRAM.
There is a conventional dual-port DRAM which employs a serial access memory for essentially carrying out the functions of the shift register described above. The serial access memory comprises serial memory cells, gates for coupling the serial memory cells to a data bus, and a pointer register for controlling the gates. According to this dual-port DRAM, it is impossible to transfer data between the serial memory cells as is done between stages of the shift register, but the functions of the serial access memory are essentially the same as those of the shift register in that the data from the serial memory cells are sequentially transferred on the data bus via the gates which are controlled by the pointer register. Accordingly, the serial access memory controls the serial input/output between the bit lines of the memory cell array and the data bus, and also the parallel input/output between the bit lines and the serial memory cells.
In the conventional dual-port DRAM which employs the serial access memory, each bit line pair corresponds one to one with a serial memory cell. For this reason, M serial memory cells are required when there are M bit line pairs in the memory cell array. Similarly, the shift register must have M stages when there are M bit line pairs in the memory cell array. But according to such a circuit construction, it is necessary to change the word construction when the word length of the serial port is changed. In other words, when the number of memory cells belonging to one word line (that is, the number of bit line pairs) is M, it is convenient when one word is formed by M bits because the serial access memory processes M bits in parallel. However, when the word length of the serial port and thus the bit length of the word which is processed is M/2, M/4, . . . , there is a problem in that it is necessary to process the data in units of two words, four words, etc.) . . . and it is inconvenient in that the word construction must be changed in order to access the memory cell array. In addition, the number of serial memory cells increases as the number of bit line pairs increases, and there is a problem in that the serial access memory inevitably occupies a large area of a memory chip. Especially in the case of a DRAM, the memory cells of the memory cell array are arranged at an extremely small pitch, and the provision of the serial access memory should not waste the reduced chip area.